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Background: The Number of transistors in recent computer chip has crossed billion mark. The VLSI design is becoming complex day by day. The Verification of such designs is a tedious process as majority of time of development is consumed in verification. Most the blocks in these chips are duplicated or replicated with some change in configuration. Verilog and System Verilog Verification Methodology doesn’t have seamless support for reusability of the verification components.
Objectives:The verification of Watchdog Timer with APB interface using UVM.
Methods: UVM Verification Methodology uses System Verilog framework to build the testbench.UVM methodology defines various verification components. The tests of sequences are kept apart from the original testbench hierarchy which helps in reusability.
Results: Watchdog timer with APB interface is designed and verification is done using UVM verification methodology. APB Write / Read and Watchdog Timer functionalities verified. Random stimulus is generated.
Conclusions: Successfully designed the Watchdog Timer with APB interface by using Verilog and simulated with the UVM based Testbench.The main advantages of this method of verification are using the virtual random coverage driven, for which the verification engineer takes minimal time for verification in the complex design system. The tests and Verification components can be reused in a different design which uses APB Interface.