Low Power Standard Logic Gate Cells Design and its Power & Delay Analysis

Abstract

This paper describes the design of a 45nm CMOS technology standard logic library cell for highly energy-efficient applications of embedded processors.Design of Inverter, NOR and NAND circuits is present in this paper to improve the speed and power. The comparative analysis of different performance parameters for CMOS logic gates is presented. Average power, Static Power and Delay are the parameters evaluated using Cadence tool. For a full-chip implementation of low-power systems operating at ultra-low voltage is feasible. The power and delay is extracted for logic cells at supply voltages 0.8 V, 1.0 V & 1.2 V at different frequencies.